Title :
Analysis of one-step majority logic decoding under correlated data-dependent gate failures
Author :
Brkic, Srdan ; Ivanis, Predrag ; Vasic, Bane
Author_Institution :
Sch. of Electr. Eng., Univ. of Belgrade, Belgrade, Serbia
fDate :
June 29 2014-July 4 2014
Abstract :
In this paper we present analysis of one-step majority logic decoders made of unreliable components in the presence of data-dependent gate failures. Gate failures are modeled by a Markov chain, and based on the combinatorial representation of the fault configurations, a closed-form expression for the average bit error rate is derived for a regular LDPC code ensemble. Presented analysis framework is then used for obtaining upper bounds on decoding performance under timing errors.
Keywords :
Markov processes; decoding; error statistics; failure analysis; logic gates; majority logic; parity check codes; Markov chain; average bit error rate; closed-form expression; correlated data-dependent gate failures; decoding performance; one-step majority logic decoding; regular LDPC code; timing errors; Bit error rate; Circuit faults; Decoding; Error probability; Logic gates; Parity check codes; Vectors;
Conference_Titel :
Information Theory (ISIT), 2014 IEEE International Symposium on
Conference_Location :
Honolulu, HI
DOI :
10.1109/ISIT.2014.6875304
