DocumentCode
1780698
Title
Optimal Selection of ATE Frequencies for Test Time Reduction Using Aperiodic Clock
Author
Gunasekar, Suriya ; Agrawal, Vishwani D.
Author_Institution
Dept. of Electr. & Comput. Eng., Auburn Univ., Auburn, AL, USA
fYear
2014
fDate
14-16 May 2014
Firstpage
52
Lastpage
56
Abstract
An aperiodic test clock methodology to reduce test time of wafer sort has been recently proposed. In practice, however, an automatic test equipment (ATE) allows only a small number of clock periods and finding those is a mathematically complex problem. This paper proposes an algorithm for optimal selection of any given number of tester clock periods.
Keywords
automatic test equipment; clocks; combinatorial mathematics; integrated circuit testing; logic testing; optimisation; sequential circuits; ATE frequency optimal selection; aperiodic test clock methodology; automatic test equipment; test time reduction; tester clock periods; wafer sort; Benchmark testing; Clocks; Graphics; Greedy algorithms; Integrated circuit modeling; Time-frequency analysis; Adaptive clocking; Aperiodic clock; Automatic Test Equipment; Scan test; Test time reduction;
fLanguage
English
Publisher
ieee
Conference_Titel
Test Workshop (NATW), 2014 IEEE 23rd North Atlantic
Conference_Location
Johnson City, NY
Print_ISBN
978-1-4799-5134-5
Type
conf
DOI
10.1109/NATW.2014.19
Filename
6875449
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