Reconfigurable digital Cartesian feedback for transmitters

This paper presents an original method to realize digital loop control for a radio communication V/UHF (Very/Ultra High Frequency) transmitter. The objective is to propose a SDR (Software Defined Radio) solution with a correction of the PA (Power Amplifier) nonlinearities. The proposed architecture is full digital solution except the up-converter for specific reasons. The used numeric core is a Virtex6 FPGA (Field Programmable Gate Array). The down-converter and loop filters are integrated in the digital part. Measurements show improvement of 5% of the EVM (Error Vector Magnitude) and more than 20 dB for the ACPR (Adjacent Channel Power Ratio) compared to the open loop. The overall delay system is about 1.4 μs and the loop gain is 20.4 dB.