Ultra Low Power Circuit Design Based on Adiabatic Logic

In this paper, four adiabatic types have been researches with TSMC 0.18 μm library, where Vin=1.8V, frequency=1MHz. We have applied the adiabatic logic structure to further reduce the power dissipation of the PBCAM. In traditional CMOS, the power dissipation mainly occurs in the MOS transistor during input data switching, however, the adiabatic logic circuit takes an opposing direction to suppress the power dissipation to zero. The experimental results show that the Quasi-1n1p based Block-XOR parameter extractor can save 0.7% in power dissipation compared to the CMOS design.