Energy efficient computing with tunnel FETs

Author

Ionescu, A.M.

Author_Institution

Nanolab, Ecole Polytech. Fed. de Lausanne, Lausanne, Switzerland

fYear

2014

fDate

20-22 Oct. 2014

Firstpage

1

Lastpage

8

Abstract

This paper reports on the state-of-the-art and recent advances concerning the tunnelling FETs as energy efficient switches, capable of operating at sub-0.5V due to their low Ioff and steep subthermal subthreshold slope (better than 60mV/decade at room temperature). Overall, it appears that the engineering of heterojunction tunnelling FETs with the application of some technology boosters similar to advanced silicon CMOS can offer the appropriate path for a high performance complementary platform for this new family of devices. More aggressive scaling of their operation voltage, below 0.1V can be achieved with new concepts like the Electron-Hole Bilayer Tunnel FET exploiting the effect of low dimensionality on the Density of States (DOS).

Keywords

energy conservation; field effect transistor switches; high electron mobility transistors; low-power electronics; silicon; tunnel transistors; CMOS; DOS; Si; density of states; electron-hole bilayer tunnel FET; energy efficient computing; energy efficient switches; heterojunction tunnelling FET; silicon; subthermal subthreshold slope; CMOS integrated circuits; Field effect transistors; Junctions; Logic gates; Performance evaluation; Silicon; Tunneling;

fLanguage

English

Publisher

ieee

Conference_Titel

Advanced Semiconductor Devices & Microsystems (ASDAM), 2014 10th International Conference on

Conference_Location

Smolenice

Print_ISBN

978-1-4799-5474-2

Type

conf

DOI

10.1109/ASDAM.2014.6998670

Filename

6998670