A new ultra low leakage and high speed technique for CMOS circuits

This paper presents a comprehensive survey and analysis of various subthreshold leakage power reduction techniques. Moreover, a new technique for low leakage and high speed is also proposed here. As the technology scales down to deep sub micron level, leakage power dissipation increases very rapidly due to the high transistor density, low threshold and ultrathin dielectric. The new proposed circuit technique includes NMOS sleep and helper transistors to reduce leakage current with appropriate W/L ratio. The proposed design gives high speed performance because it includes NMOS transistor in the design which is having higher electron mobility. Post layout simulation of XOR gate using microwind tool with 45nm Berkeley predictive technology model shows that the new circuit technique achieves significant power reduction during a standby mode with lesser delay.