Design and evaluation of low power and high speed logic circuit based on the modified gate diffusion input (m-GDI) technique in 32nm CNTFET technology

Speed, power and chip area are the crucial parameters in logic circuit designs. With the gate diffusion input (GDI) technique, low power logic gates can be designed with the minimum number of transistors. In this paper the modified GDI (m-GDI) cell based on the basic GDI cell is proposed for designing the logic circuits in nano process. In the proposed GDI cell, the chip area for the pull up and pull down networks are reduced about 80% and 50%, respectively, in comparison with the basic GDI cell. Also power delay production (PDP) has improved in this design. The simulation is done in 32nm technology with H-SPICE software under the condition of 0.9V supply voltage, and 500MHz frequency.