Low power adiabatic logic using DCPAL block

This paper presents low power Differential Cascode and Pre-resolved Adiabatic Logic (DCPAL) in 3 different proposed structures (DCPAL termination block, common input DCPAL block, and stepwise DCPAL block) which has low energy dissipation compared to 2N-2N2P termination block. This is achieved by replacing the low power 2N-2N2P logic in 2N-2N2P termination block by DCPAL structures. DCPAL structures are cascaded with different styles such as DCPAL termination block, common input DCPAL block, and stepwise DCPAL block. Simulation in Cadence virtuoso environment using 0.18 μm UMC CMOS process shows that proposed circuits have 35% to 92% lesser energy dissipation compared to 2N-2N2P termination block for frequency range 83 KHz to 125 MHz. The simulations have been carried out at a voltage ranging between -1.8 V to 1.8 V.