A novel power-efficient architecture for high-speed flash ADCs

In this paper, a new architecture for a low-power highspeed Flash Analog-to-Digital Converter (ADC) is presented. Unlike conventional Full-Flash architecture in which power consumption is increased exponentially with the increase of resolution, in this proposed architecture, power consumption varies approximately linearly with the growth of resolution. In fact, by taking advantage of initial intelligent comparison, the number of required preamplifiers and latches are significantly reduced. Besides, by using simple logic gates, many additional circuitries such as complicated encoder and bubble-error correction circuits have been avoided. As a result, minimum power consumption would be achieved. The operation of the proposed ADC has been verified in both systematic and circuit-level implementation. Simulation results of a 6-bit 1GS/s Flash ADC in 0.18μm CMOS technology reveals that in compare with the conventional architecture, power is saved to more than 70%. At Nyquist sampling rate, ADC has the total harmonic distortion (THD) of -34dB and FOM of 0.2pJ/conversion at supply voltage of 1.8V.