Design of CAD ASIP for JIT extensible processor: Case study on simulated annealing placer

Dynamic Reconfigurable computing platform using embedded Just-In-Time (JIT) compilation is the most flexible platform among others. In these systems all complex kernels can be translated to bitstream to be executed on hardware part (FPGA) using an embedded processor which are dedicated general processor. Executing the CAD algorithms on embedded processor is too time-consuming and normally is not feasible for real applications. In this paper, application-specific instruction set processor (ASIP) has proposed as a promising solution to meet this requirement. A novel design of an ASIP is presented tailored for CAD algorithms. As a case study, Simulated Annealing (SA) placer is implemented and detailed. Experimental results show our CAD ASIP achieves 22X speed up in execution time in cost of 3% overhead in logic gates.