A 68.8ps jitter, 1.685mw band-selective reconfigurable DCO design for overlapped and non-overlapped applications in 180nm

Digitally controlled Oscillators used in All Digital PLL. They are main responsible for range of frequency and power consumption in ADPLL. In the Conventional DCO designs, DCO work in one single band. We recommend in this paper presents a new approach on the design of DCO working in band selective reconfigurable mode with control logics. This design allows using DCO in low-frequency low-power applications and switch to higher frequencies with higher power and we can trade of between power-performance and output frequency. The proposed design is based on using digitally controlled capacitors, current starving and low-power Schmitt triggers in critical points of the DCO loop while keeping the coarse and fine tunings. The delay nonlinearity factors are clearly checked and resolved with using a new combined logic control. The proposed designs are evaluated in 180nm CMOS for 64 input coarse code. Our experimental results show that the band selective reconfigurable with overlap mode DCO consumes about 1.6845mW at 184.61MHz with measured 68.7ps jitter and band selective reconfigurable without overlap mode DCO consumes about 1.7844 mW at 137.36 MHz with measured 111.4ps jitter. Band selective reconfigurable DCO design is suitable for Reconfigurable and multi-standard ADPLL designs.