Improved fault-tolerance through dynamic modular redundancy (DMR) on the RISA FPGA platform

Autonomously fault-tolerant systems have received a renewed interest for the design of dependable computing systems with the increasing requirements of a variety of critical applications including deep space probes, satellites, reactor control systems, and Internet-of-Things applications including health and environment monitoring. Autonomous fault-tolerant systems are based on hardware capable of self-monitoring and self-repair. In this context, this paper investigates the use of fine-grained, partial dynamic reconfiguration on FPGA for achieving a higher degree of fault-tolerance with lower permanent overhead than TMR, its potential use for long term system maintenance and its capability of detecting faults quickly. The case study shown in this paper focuses mainly on accelerating fault-detection trough optimising a fault-monitoring strategy using an evolutionary algorithm (EA).