Design of ultra-low-power CMOS amplifiers based on flicker noise reduction

In this paper, a weak inversion technique for recycling folded cascode (RFC) and folded cascode (FC) operational amplifier design with flicker noise reduction is presented. Flicker noise is the dominant noise source in silicon MOSFET´s especially in low frequency. A new formulation for input referred flicker noise in weak inversion region is also presented and an efficient tradeoff between input refereed flicker noise power and frequency response is performed for optimum design in weak inversion region. This procedure will be useful for all of CMOS weak inversion amplifiers. The proposed technique significantly enhances the conventional noise performance of FC and RFC amplifier. The theoretical analysis is verified in 0.18 μm CMOS technology.