DocumentCode :
1785571
Title :
Broadband FPGA payload processing in a harsh radiation environment
Author :
Rittner, Florian ; Glein, Robert ; Kolb, Thomas ; Bernard, Benjamin
Author_Institution :
RF & Microwave Design Dept., Fraunhofer Inst. for Integrated Circuits, Erlangen, Germany
fYear :
2014
fDate :
14-17 July 2014
Firstpage :
151
Lastpage :
158
Abstract :
In this paper, we propose a concept for broadband Digital Signal Processing under consideration of mitigation schemes to increase the reliability. We take Single Event Upsets into account to guarantee a reliable operation during a In-Orbit-Verification. It will be performed on the Fraunhofer On-Board Processor, which is a dynamically reconfigurable On-Board Processor platform based on two space-grade Virtex-5QV FPGAs. A master and slave FPGA concept enables broadband Digital Signal Processing experiments, which are controlled and monitored by the high reliable master FPGA. Each FPGA processes a separated signal path of the Fraunhofer On-Board Processor. The first FPGA executes scrubbing of both FPGAs, measures the current radiation and observes the whole system with a fault management. The second FPGA realizes only the broadband Digital Signal Processing, which results in more usable resources. We analyze the impact of the radiation to point out the influence to the FPGAs. A case study demonstrates a Digital Down Converter for broadband Digital Signal Processing. This hardware verification evaluates a 306 Mbit/s broadband signal, modulated with Quadrature Phase-Shift Keying. It results in a Signal-to-Noise Ratio of 19.29 dB. Due to separation of mitigation schemes and broadband Digital Signal Processing the system operates reliable and the resources are used efficient.
Keywords :
fault tolerant computing; field programmable gate arrays; microprocessor chips; phase shift keying; reconfigurable architectures; reliability; signal processing; Fraunhofer onboard processor; broadband FPGA payload processing; broadband digital signal processing; broadband digital signal processing experiments; digital down converter; dynamically reconfigurable onboard processor platform; fault management; harsh radiation environment; in-orbit-verification; master and slave FPGA concept; phase-shift keying; signal-to-noise ratio; single event upsets; space-grade Virtex-5QV FPGA; Broadband communication; Computer architecture; Digital signal processing; Field programmable gate arrays; Reliability; Satellites; System-on-chip;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Adaptive Hardware and Systems (AHS), 2014 NASA/ESA Conference on
Conference_Location :
Leicester
Type :
conf
DOI :
10.1109/AHS.2014.6880171
Filename :
6880171
Link To Document :
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