NBTI aware IG-FinFET based SRAM design using adaptable trip-point sensing technique

The progressive scaling demands effort from both the circuit and the device level, to cope with circuit variability and reliability issues. Advent of FinFET technology has suppresses the short channel effects and variability, but still suffers with self heating problem consequently increases temporal degradations. In this paper, we investigate severity of Negative Bias Temperature Instability (NBTI) and proposes an adaptable trip point sensing based compensation technique to satisfy performance metrics for NBTI aware Independent Gate (IG) FinFET based SRAM. Simulation results are carried out using HSPICE with PTM 32nm IG-FinFET technology demonstrate that threshold voltage deviates from its nominal value by 17%, causing 6% and 13% degradation in SNM and RNM, respectively under NBTI degradation at 125°C for 3 years. The proposed technique yields 42% reduced read failures under NBTI. Thus, proposed approach improves the stability of SRAM array during its operational life and hence, reliability of the system.