Probability density function based reliability evaluation of large-scale ICs

For the current advanced technology nodes, an accurate, yet fast reliability analysis is needed at design time, to enable the comparison between different circuit architectures, and thus a reliability-aware design and synthesis process. To this end we propose a reliability assessment framework that is able to estimate more accurately the circuit reliability and which can be applied to large-scale circuit settings, by: (i) taking into account the circuit topology (and implicitly its reconvergent fanouts), the input vectors, the environmental conditions and fault scenarios, (ii) employing a range of probabilities, i.e., a Probability Density Function (PDF), instead of hitherto single probability value, in order to quantify the circuit reliability, (iii) employing variational inference, to derive the circuit primary output PDFs, given its primary inputs PDFs, and (iv) adapting the traditional variational inference approach to exploit the peculiarities of the probabilistic model afferent to logic circuits, for convergence speed improvements and thus applicability in large scale circuits settings.