Integration of threshold logic gates with RRAM devices for energy efficient and robust operation

Differential mode threshold-logic gates can be programmed to compute complex logic functions within a single cell, resulting in significant reduction in area and power. However the circuit yield reduces if they are operated at low voltages. This paper describes a novel integration of RRAM with such threshold-logic gates to achieve robust, low voltage (0.6V for 65nm technology) and energy efficient computation of threshold-logic functions. Below 0.6V, we observed that the performance(and thereby, energy delay product) of conventional CMOS circuits degrades substantially compared to the proposed threshold-logic circuits. The improvement in performance and energy of the new circuit architecture are demonstrated while considering process variations in both the MOSFET and RRAM devices. For each threshold function implementable by threshold-logic gate, comparison of energy, delay and energy delay product with equivalent CMOS implementation is given. The advantages in area, energy and delay of threshold logic implementations over conventional CMOS logic gates is demonstrated by two commonly used functional components.