The Impact of Substrate Bias on the Steep Subthreshold Slope in Junctionless MuGFETs

The impact of substrate bias VBS on the steep subthreshold slope (S-slope) in junctionless (JL) multiple gate MOSFETs has been analyzed experimentally. JL transistors with fin width of 40 nm and five parallel fins exhibit an S-slope of 20 mV/decade and an ON/OFF current ratio of up to 4.5×10⁴ at VDS=1.6 V and VBS=0 V. The S-slopes were decreased due to an increase of impact ionization as the positive VBS increased. When VBS is increased from 0 to 25 V, the S-slope is decreased from 20 to 6 mV/decade. The supply voltage can be reduced with the application of a positive VBS. The dependence of the steep S-slope on VBS been analyzed for different fin widths and fin numbers. To evaluate the device reliability of JL transistor, the shifts in the threshold voltages and the S-slopes were measured. 3-D device simulations have been performed to explain the measured results.