An efficient hardware architecture for stereo disparity estimation

Author

Joseph, Friedel ; Francis, Kiran ; Hore, Alain ; Roy, Sandip ; Josephine, S. ; Paily, Roy P.

Author_Institution

IIT Guwahati, Guwahati, India

fYear

2014

fDate

16-18 July 2014

Firstpage

1

Lastpage

6

Abstract

This paper presents an architecture for disparity estimation in real time which is designed to be used in a blind navigation assistance system. A highly pipelined hardware prototype has been designed and verified. Sum of Absolute Difference (SAD) algorithm is chosen as the cost function in the proposed architecture. The major design consideration is efficient hardware utilization and high throughput. This system is designed to support video resolutions upto 2048 × 2048 at high frame rates. The performance evaluation shows very low latency even at low processing frequency.

Keywords

handicapped aids; image resolution; stereo image processing; video signal processing; SAD algorithm; blind navigation assistance system; cost function; hardware architecture; high frame rates; low latency; low processing frequency; performance evaluation; pipelined hardware prototype; stereo disparity estimation; sum of absolute difference algorithm; video resolutions; Algorithm design and analysis; Computer architecture; Estimation; Field programmable gate arrays; Hardware; Pipelines; Stereo vision;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Design and Test, 18th International Symposium on

Conference_Location

Coimbatore

Print_ISBN

978-1-4799-5088-1

Type

conf

DOI

10.1109/ISVDAT.2014.6881049

Filename

6881049