An approach for efficient FIR filter design for hearing aid application

In this paper, a constant coefficient finite impulse response (FIR) filter design has been proposed for hearing aid application. The major change in the proposed architecture is the use of 4:2 compressors instead of using adders. The 17 order filter for hearing aid has been realized at gate level using Verilog HDL. The architectures have been implemented in UMC 90nm technology by the use of Cadence RTL compiler. Synthesis results of the proposed architecture show an improvement of 39.4% and 11.34% in speed and area respectively as compared to the recently published architecture. The proposed architecture provides significant gain of 46.3% in area-delay product (ADP) and 23.7% in power-delay product (PDP). Finally, the functionality of the architecture has been verified by Altera DSP Builder tool.