A novel architecture for QPSK modulation based on time-mode signal processing

With shrinking process technology, the scale of integration has increased significantly for digital design. Therefore, the increase in operating frequency, and attempt to reduce area and power has been addressed to large extent. On the contrary, it has lesser impact on its analog counterpart and has not been able to catch up with the respective design metrics pertaining to digital design. This paper presents a new design method for Quadrature Phase Shift Keying (QPSK) modulation technique using Time Mode Signal Processing (TMSP) technique. This method uses a digital clock signal acting as the carrier signal and thus provides a digital interface at the output. A 2 bit input digital code modulates the delay of the clock and hence carries the information in it. The proposed design yields a low voltage and low power alternative to its known analog counterparts. We implemented the design using 0.18μm TSMC CMOS technology. The power supply is kept at 2V, while the carrier frequency remains 250MHz. The results for both pre and post-layout simulations yield significant improvement in layout area, power dissipation and signal-to-noise ratio (SNR) as compared to a conventional design for QPSK modulation.