An FPGA implementation of image signature based visual-saliency detection

In this paper we present a prototype FPGA design for Saliency detection based on image signature technique to support embedded vision application. Visual attention supports biological vision to restrict our gaze only to the region of interest of a visual scene. We propose a pipelined architecture using Gaussian filter, Discrete Cosine Transform, Inverse Discrete Cosine Transform and Averaging block that is shared across the system. The investigation involves simulation and synthesis of VHDL code using ModelSim^TM and Xilinx Synthesis Toolbox as design environments. Due to real-time requirements and computational-cost constraints in embedded systems, it is necessary to accelerate Saliency detection algorithm by hardware implementation. Experiment shows that the proposed hardware has the maximum clock speed of 160 MHz with Xilinx ML510 (Virtex-5 FX130T) FPGA platform.