An empirical delta delay model for highly scaled CMOS inverter considering Well Proximity Effect

Author

Dalai, Bijay Kumar ; Karnnan, N. ; Sharma, Ashok ; Anand, B.

Author_Institution

Dept. of Electron. & Commun. Eng., Indian Inst. of Technol. Roorkee, Roorkee, India

fYear

2014

fDate

16-18 July 2014

Firstpage

1

Lastpage

2

Abstract

As the semiconductor industry is moving down to deep-sub micron era (below 45nm), Well Proximity Effect (WPE) is causing significant variations in device performance. This may impact the functionality and performance of circuit designs in highly scaled CMOS technologies. In this work, we have studied the impact of WPE on standard cells and propose an empirical delta-delay model for an inverter in 28nm technology node as a function of well to poly edge distance. Our model can be extended for other standard cells and can be used for context aware standard cell library characterization considering WPE.

Keywords

CMOS integrated circuits; delays; integrated circuit design; integrated circuit modelling; invertors; proximity effect (lithography); WPE; circuit design; deep-sub micron era; empirical delta delay model; highly scaled CMOS inverter; semiconductor industry; size 28 nm; standard cell library characterization; well proximity effect; CMOS integrated circuits; Data models; Delays; Inverters; Load modeling; Semiconductor device modeling; Standards; CMOS inverter; Delta delay model; Timing variations; Well Proximity Effect (WPE);

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Design and Test, 18th International Symposium on

Conference_Location

Coimbatore

Print_ISBN

978-1-4799-5088-1

Type

conf

DOI

10.1109/ISVDAT.2014.6881062

Filename

6881062