Power optimized PLL implementation in 180nm CMOS technology

Author

Sreehari, Patri ; Devulapalli, Pavankumarsharma ; Kewale, Dhananjay ; Asbe, Omkar ; Krishna Prasad, K.S.R.

Author_Institution

Nat. Inst. of Technol., Warangal, India

fYear

2014

fDate

16-18 July 2014

Firstpage

1

Lastpage

2

Abstract

This paper describes the design of power optimized phase locked loop for frequency synthesis, Clock and Data recovery, carrier synchronization and many more communication and VLSI applications. PLL consist of Phase Frequency Detector, charge pump along with passive low pass filter and wide tuning VCO. A modified ring oscillator with tuning range of 280 MHz to 2.47GHz and phase noise of -112.4dBc/Hz at 1MHz offset is designed. Frequency Detector consist of DFF along with CMOS gates with low power architectures. Traditional charge pump, passive low pass filter, modified ring oscillator and divider for frequency synthesis offers less power and system noise. PLL proposed here has lock in range from 500MHz to 1GHz with output frequency ranging from 1GHz to 2GHz, maximum pull in time of 244ns and maximum power consumed is 252μW at 2GHz.

Keywords

CMOS analogue integrated circuits; VLSI; charge pump circuits; clock and data recovery circuits; frequency synthesizers; integrated circuit design; integrated circuit noise; low-power electronics; phase locked loops; phase noise; synchronisation; voltage-controlled oscillators; CMOS gates; CMOS technology; DFF; VLSI application; carrier synchronization; charge pump; clock and data recovery; divider; frequency 280 GHz to 2.47 GHz; frequency detector; frequency synthesis; low-power architectures; modified ring oscillator; passive low-pass filter; phase frequency detector; phase noise; power 252 muW; power-optimized PLL implementation; power-optimized phase-locked loop design; size 180 nm; system noise; time 244 ns; wide-tuning VCO; Charge Pump (CP); Loop Filter; Phase Frequency Detector (PFD); Phase Locked Loop (PLL); Pull-in Time; Voltage Controlled Oscillator (VCO);

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Design and Test, 18th International Symposium on

Conference_Location

Coimbatore

Print_ISBN

978-1-4799-5088-1

Type

conf

DOI

10.1109/ISVDAT.2014.6881065

Filename

6881065