Hardware accelerator for real-time image resizing

An accurate, hardware efficient and fast image rescaling unit is a crucial part of any real-time image processing system. Although there are a number of image scaling algorithms existing in the literature but Bicubic and Bilinear interpolation algorithms are most widely used. In the recent years, numerous algorithms have been proposed that aim to bridge the gap between these two standard algorithms, by attempting to provide high image quality of the former while maintaining the computational simplicity of the latter. This paper proposes a novel image resizing algorithm which uses a four-part piecewise linear function that closely mimics the behavior of the bicubic kernel, and thus provides high quality resized images comparable to Bicubic interpolation while having a much lower computational cost. An optimized architecture is proposed to implement this algorithm which features a high re-use of hardware units for coefficient generation so that the hardware cost is comparable to that of bilinear interpolation. The architecture and algorithm have been designed in tandem so as to meet the real-time requirements of applications such as automated video surveillance, requiring minimal hardware use without compromising on image quality.