VLSI design of fast fractal image encoder

A fast search based architecture for fractal image encoder, which efficiently exploits parallelism, is proposed. Speed up in encoding is achieved through parallel processing by finding data independency in different mathematical operations carried out in fractal encoding. This architecture requires 531 milli seconds to encode a 256×256 gray scale image at maximum clock frequency of 73.11 MHz. Thus, proposed architecture can be considered as a successful approach for real time application for image compression.