Design of sequential circuits using single-clocked Energy efficient adiabatic Logic for ultra low power application

Author

Chanda, Manash ; Chakraborty, A.S. ; Nag, Sudip ; Modak, R.

Author_Institution

ECE Dept., Meghnad Saha Inst. of Technol., Kolkata, India

fYear

2014

fDate

16-18 July 2014

Firstpage

1

Lastpage

2

Abstract

This paper presents energy efficient pre-settable adiabatic sequential circuits based on the Energy efficient adiabatic Logic (EEAL). Adiabatic Flip-flops and sequential circuits have been implemented using EEAL style in a TSMC 0.18 μm CMOS technology. Extensive CADENCE simulations show that EEAL based sequential circuit consumes only 22%-35% of total energy consumed by others imperative logic styles.

Keywords

CMOS logic circuits; flip-flops; logic design; low-power electronics; sequential circuits; CADENCE simulations; EEAL-based sequential circuit; TSMC CMOS technology; adiabatic flip-flops; energy efficient pre-settable adiabatic sequential circuits; imperative logic styles; sequential circuit design; single-clocked energy-efficient adiabatic logic; ultralow-power application; CMOS integrated circuits; Clocks; Energy efficiency; Flip-flops; Logic gates; Radiation detectors; Sequential circuits; Adiabatic logic; Pre-settable flip-flops; adiabatic counter; energy efficient; single-clock;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Design and Test, 18th International Symposium on

Conference_Location

Coimbatore

Print_ISBN

978-1-4799-5088-1

Type

conf

DOI

10.1109/ISVDAT.2014.6881076

Filename

6881076