Title :
An ASIP approach for interpolation performance enhancement in HEVC decoder
Author :
Lee Minkyu ; Song Yong Ho ; Chung Ki-Seok
Author_Institution :
Dept. of Electron. & Comput. Eng., Hanyang Univ., Seoul, South Korea
Abstract :
In this paper, an application-specific instruction-set processor (ASIP) implementation for interpolation operation for high efficiency video coding (HEVC) decoders is proposed. HEVC is a new video compression standard that has higher compression efficiency than the previous ones. The proposed ASIP is implemented on the XRC_D2MR processor by augmenting the instruction set architecture in Xtensa Tensilica processor using Tensilica instruction extension (TIE).
Keywords :
application specific integrated circuits; data compression; decoding; interpolation; microprocessor chips; video coding; ASIP approach; HEVC decoder; TIE; Tensilica instruction extension; XRC_D2MR processor; Xtensa Tensilica processor; application-specific instruction-set processor; high efficiency video coding; instruction set architecture; interpolation performance enhancement; video compression standard; Decoding; Interpolation; Logic gates; Random access memory; Registers; Software; Video coding; ASIP; HEVC; interpolation; motion compensation;
Conference_Titel :
Network Infrastructure and Digital Content (IC-NIDC), 2014 4th IEEE International Conference on
Conference_Location :
Beijing
Print_ISBN :
978-1-4799-4736-2
DOI :
10.1109/ICNIDC.2014.7000300
