DocumentCode :
1786696
Title :
Validation of SoC firmware-hardware flows: Challenges and solution directions
Author :
Abarbanel, Yael ; Singerman, Eli ; Vardi, Moshe Y.
Author_Institution :
Intel Corp., Hillsboro, OR, USA
fYear :
2014
fDate :
1-5 June 2014
Firstpage :
1
Lastpage :
4
Abstract :
In SoC, key infrastructure/backbone flows are distributed across many IPs and involve tight firmware and hardware interaction. Examples include resets, power management, security, and more. Traditional hardware validation techniques are no-longer adequate for such flows, due to the short time-to-market requirements, in particular, for mobile devices. In this paper, we articulate the challenges and discuss a few solution directions that are being pursued in this space at Intel.
Keywords :
firmware; hardware-software codesign; mobile handsets; system-on-chip; IP; Intel; SoC firmware-hardware flows; firmware-hardware interaction; hardware validation techniques; infrastructure-backbone flows; mobile devices; power management; time-to-market requirements; Emulation; Field programmable gate arrays; IP networks; Protocols; Security; Silicon; System-on-chip; Debug; Emulation; FPGA; Flows; Formal Analysis; Hardware-Software co-validation; Simulation; SoC; Validation; Virtual Platform;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Design Automation Conference (DAC), 2014 51st ACM/EDAC/IEEE
Conference_Location :
San Francisco, CA
Type :
conf
DOI :
10.1145/2593069.2596692
Filename :
6881329
Link To Document :
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