Title :
FALCON: A framework for hierarchical computation of metrics for component-based parameterized SoCs
Author :
Javaid, H. ; Yachide, Yusuke ; Shwe, Su Myat Min ; Bokhari, Haseeb ; Parameswaran, Sri
Author_Institution :
Sch. of Comput. Sci. & Eng., Univ. of New South Wales, Sydney, NSW, Australia
Abstract :
In this paper, we focus on systematic and efficient computation (accurate value or an estimate) of metrics such as performance, power, energy, etc. of a component-based parameterized system-on-chip (SoC). Traditionally, given models of SoC components (such as cycle-accurate simulator of a processor, trace-based simulator of a cache/memory), a designer manually determines an execution schedule of these models (such as execute processor simulator, followed by cache/memory simulator) to combine/propagate their individual results for computation of a SoC metric. To reduce designer´s effort, we propose FALCON, a framework where the execution schedule of component models is generated automatically, and a minimal number of model executions is used to compute values of a SoC metric for the given component models and design space (resulting from component parameter values). FALCON is semi-automated, is applicable to a wide range of SoC platforms with ease, and works with existing design space exploration algorithms. In three case studies (uniprocessor system, multiprocessor pipeline system and multiprocessor mesh network-on-chip system), FALCON reduced designer´s effort (measured in minutes) by at least two orders of magnitude.
Keywords :
multiprocessing systems; network-on-chip; processor scheduling; FALCON-based parameterized SoC; SoC metric; automatic execution schedule generation; component model execution; component parameter values; component-based parameterized system-on-chip; cycle-accurate processor simulator; design space exploration algorithms; framework-for-hierarchical computation-of-metrics-for-component; multiprocessor mesh network-on-chip system; multiprocessor pipeline system; semiautomated FALCON; trace-based cache simulator; trace-based memory simulator; uniprocessor system; Analytical models; Clocks; Computational modeling; Estimation; Integrated circuit modeling; System-on-chip;
Conference_Titel :
Design Automation Conference (DAC), 2014 51st ACM/EDAC/IEEE
Conference_Location :
San Francisco, CA
DOI :
10.1145/2593069.2593138