DocumentCode
1786753
Title
Modeling parasitic capacitances in Gallium Nitride (GaN) FET transistor
Author
Loo-Yau, J.R.
Author_Institution
Centro de Investig. y de Estudios Av. del I. P. N. Unidad Guadalajara (Cinvestav-GDL), Zapopan, Mexico
fYear
2014
fDate
12-14 Nov. 2014
Firstpage
1
Lastpage
6
Abstract
In this paper an effective method for modeling parasitic capacitances of Gallium Nitride (GaN) FET transistors is presented. The proposed method is a modification of a method that was proposed for Gallium Arsenide (GaAs) transistors. The modification consists of the computation of a constant relating to the asymmetry of the transistor when it is pinched-off. Experimental data, up to 50 GHz, show the effectiveness of the proposed method by comparing it with traditional methods.
Keywords
III-V semiconductors; gallium compounds; microwave field effect transistors; semiconductor device models; wide band gap semiconductors; FET transistor; GaN; frequency 50 GHz; linear modelling; parasitic capacitances; parasitic elements; Capacitance; Field effect transistors; Gallium arsenide; Gallium nitride; Integrated circuit modeling; Silicon compounds; FET linear modeling; GaN FET transistor; parasitic elements;
fLanguage
English
Publisher
ieee
Conference_Titel
Central America and Panama Convention (CONCAPAN XXXIV), 2014 IEEE
Conference_Location
Panama City
Type
conf
DOI
10.1109/CONCAPAN.2014.7000417
Filename
7000417
Link To Document