Increased reliability of communication systems in sub-threshold region implementations with pulsed-latch registers

For development of digital circuits in deep submicron, that are widely used in communication systems, vulnerability to soft error has become a critical consideration. Also with increasing complexity and number of transistors, energy consumption increases significantly. Transition to sub-threshold supply voltage regions is a popular way to remedy this issue. We address these two issues with our solution in digital communication systems. In this paper, a pulsed-latch is proposed to increase immunity of communication systems against single event effect in sub-threshold region. For this purpose, a new transition detector is designed in order to detect single event transitions. It shows significant improvements in terms of performance, power, and area. This design is implemented in 90nm CMOS technology at 0.3V power supply. The delay and power is reduced respectively ∼44%–140% and 4.9–7.6 times compared to conventional transition detectors. This circuit is embedded into our latch to be used as a register. To prove the effectiveness of the method, performance by proposed pulsed-latch is compared with that of a conventional reliable register. Also, it is replaced by a conventional flip-flop in a butterfly computation block which is used in a Fast Fourier Transform (FFT) accelerator engine to verify functionality and performance.