Components for Coverage-Driven Verification of floating-point units

This work presents the application of a mixed strategy that combines Constrained Random Tests (CRT) and Coverage Driven Verification (CDV) as well as the development of a coverage model for Floating Point Unit (FPU) designs. The proposed strategy is materialized in two key verification components for functional verification: an input generator and a verification monitor. The generator module creates random input operands based on constraints for each operation. The monitor component not only checks the result but also indicates which cases have not been tested and estimates how much of the design functionality has been tested. Tests show that using CRT-only strategy the functional does not reach the complete coverage. However, using the proposed coverage driven verification approach not only reaches 100% coverage but also speeds up the verification up to 4.5x.