PUF´s performance evaluation among different Xilinx FPGAs families

The FPGAs have been used as a platform to implement and validate the Physical Unclonable Function con-structions. The authors validate PUFs performance using several know metrics (reliability, uniqueness, uniformity, and bit aliasing) and these test are conducted just on the FPGA used to the implementation. The problem arises when we want to use a PUF tested on a specific FPGA family into another, there is no assurance that the behavior of a PUF is the same among different families of FPGA. Up to our knowledge no previous work has been reported to evaluate PUF designs for different FPGA families and manufacturing technology. Additional, in this paper we proposed three PUF schemes based in the combination of two previous PUFs designs: BUT and LUT. All schemes were implemented and evaluated with main PUF metrics, on Spartan-3E, Spartan-6, and Virtex-5. An analysis of the results allows us to determine which FPGA platform have good behavior and what is the performance impact by the environmental variations.