On the design of hazard free reversible asynchronous circuits

Asynchronous systems are designed without any global clock signal. Here computation is achieved by a series of events represented by signal transition edges; hence the speed of computation is determined by the signal propagation delay of the asynchronous circuit and not on the global clock. Some notable problems in synchronous circuit design due to higher performance demand are clock skew, power dissipation and worst case performance. The asynchronous circuit design which generally does not suffer from these problems, is experiencing a significant resurgence of interest and research activity. In this work, we propose analysis and design of reversible Hazard free latches for the first time in Reversible literature. Two methods are proposed for static hazard removal. Then performance parameters of these two methods are then compared. We also propose design of 4-bit up/down Asynchronous counter. All the proposed designs are functionally verified using Xilinx ISE simulator with their designs coded in the Verilog HDL.