A novel design of cascading serial bit-stream magnitude comparator using QCA

The IC technology is tremendously growing day by day to improve the performance of the circuits structure in a compact and high density form. This tiny IC arena started and introduced the Quantum-dot cellular Automata (QCA) to overcome the pitfalls of conventional CMOS technology throughput. In order to bring a new phase of IC design in an optimized & efficient manner, we proposed, cascading serial bit stream comparator with majority voter and inverter using QCA technology. The proposed method shows comparatively better results in terms of the number of gates & clock zones. The obtained result shows that 28% of logic gate area is saved compared to the conventional design. Further, it requires less number of gates for cascading to compare the two n-bit numbers.