DocumentCode :
1789461
Title :
All-bit-line MLC flash memories: Optimal detection strategies
Author :
Xiujie Huang ; Asadi, Meysam ; Kavcic, Aleksandar ; Santhanam, Narayana
Author_Institution :
Dept. of Comput. Sci., Jinan Univ., Guangzhou, China
fYear :
2014
fDate :
10-14 June 2014
Firstpage :
3883
Lastpage :
3888
Abstract :
We are concerned with the optimal detector design for the all-bit-line MLC flash memory. We provide a channel model of the MLC flash memory, where the channel parameters are mathematically tractable. Then we present an optimal maximum a-posteriori sequence detector. The optimal detector can be executed over a trellis whose branch metrics can be computed by using Fourier transforms of analytically computable characteristic functions (corresponding to likelihood functions). The soft-output detectors for both simple one-dimensional channel models and more realistic page-orientated two-dimensional channel models are derived. Simulation results show not only that the soft-output detector has the same hard-output bit-error-rate performance as some previously known detectors did, but that the soft-output detector outperforms previously known detectors by a gain of 0.23 dB.
Keywords :
Fourier transforms; circuit optimisation; detector circuits; flash memories; maximum likelihood estimation; 1D channel models; Fourier transforms; all-bit-line MLC flash memories; gain 0.23 dB; hard-output bit-error-rate performance; multilevel cell; optimal detection strategies; optimal detector design; optimal maximum a-posteriori sequence detector; page-orientated 2D channel models; soft-output detectors; Ash; Channel models; Computer architecture; Detectors; Measurement; Microprocessors; Noise;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Communications (ICC), 2014 IEEE International Conference on
Conference_Location :
Sydney, NSW
Type :
conf
DOI :
10.1109/ICC.2014.6883927
Filename :
6883927
Link To Document :
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