DocumentCode
1790248
Title
A FPGA based real-time post-processing architecture for active stereo vision
Author
Seung-min Choi ; Jiho Chang ; Dae Hwan Hwang
Author_Institution
Dept. of IT convergence Technol. Res., Electron. & Telecommun. Res. Inst., Daejeon, South Korea
fYear
2014
fDate
22-25 June 2014
Firstpage
1
Lastpage
2
Abstract
This paper presents a post-processing architecture for high quality depth map in active stereo vision. The proposed architecture consists of five sub-blocks in cascade manner, which are consistency check, hole filling, variance check, weighted median filter, and joint bilateral filter. The novel design which is implemented on a single FPGA achieves 60 frames per second for 1280×720 stereo images with 256 disparity range.
Keywords
active vision; computer architecture; field programmable gate arrays; median filters; real-time systems; stereo image processing; FPGA; active stereo vision; consistency check; high quality depth map; hole filling; joint bilateral filter; real-time post-processing architecture; stereo images; variance check; weighted median filter; Field programmable gate arrays; Filling; Hardware; Joints; Matched filters; Real-time systems; Stereo vision; FPGA; disparity filter; post processing; stereo vision;
fLanguage
English
Publisher
ieee
Conference_Titel
Consumer Electronics (ISCE 2014), The 18th IEEE International Symposium on
Conference_Location
JeJu Island
Type
conf
DOI
10.1109/ISCE.2014.6884341
Filename
6884341
Link To Document