• DocumentCode
    1790457
  • Title

    An efficient check node operation circuit for Min-Sum based LDPC decoder

  • Author

    Keol Cho ; Ki-Seok Chung

  • Author_Institution
    Dept. of Electron. Comput. Eng., Hanyang Univ., Seoul, South Korea
  • fYear
    2014
  • fDate
    22-25 June 2014
  • Firstpage
    1
  • Lastpage
    2
  • Abstract
    This paper presents a low power and area-efficient check node operation circuit for LDPC decoders based on Min-Sum algorithm. By improving a heavily used comparator circuit, our proposed check node unit reduces area and power consumption by 8% and 13%, respectively, without decoding speed degradation compared to conventional LDPC decoders.
  • Keywords
    codecs; comparators (circuits); low-power electronics; parity check codes; LDPC decoders; check node operation circuit; comparator; min-sum algorithm; power consumption; Algorithm design and analysis; Computer architecture; Decoding; Hardware; Iterative decoding; Power demand; LDPC decoder; circuit size; low power; low-density parity-check codes;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Consumer Electronics (ISCE 2014), The 18th IEEE International Symposium on
  • Conference_Location
    JeJu Island
  • Type

    conf

  • DOI
    10.1109/ISCE.2014.6884452
  • Filename
    6884452
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1790457