Study of gate all around InAs/Si based nanowire FETs using simulation approach

In this paper, a gate-all-around Si Nanowire FET (NWFET) and InAs NWFET have been studied and compared with respect to various performance parameters. The device metrics considered at the nanometer scale are transfer characteristics, transconductance, output characteristics, drive and leakage current, switching speed (Ion/Ioff), conduction-band profile, subthreshold swing (SS) and drain induced barrier lowering (DIBL). It has been shown that InAs channeled NWFET has higher mobility and hence higher transconductance, whereas Si NWFET shows better immunity towards short channel effects with lower leakage current, lower sub-threshold slope, lower DIBL. Therefore, Si NWFET appears to be applicable for Low Operating Power applications whereas, InAs with its high ON currents and switching speeds prove to be a good candidate for high performance applications of the long term ITRS where reasonably high leakage currents are acceptable as a trade off for increased operating speeds.