Low power design and analysis of fundamental logics using adiabatic array logic

With the advent of adiabatic logic, the MOS-based digital circuit design has shown improvement by leaps and bounds in terms of reducing power. In the same quest, an adiabatic logic family called the Adiabatic Array Logic is used to design some fundamental logic gates- NOT, NAND, NOR and XOR, which shows significant improvement in power dissipation over the static CMOS logic style. Moreover, these proposed circuits also show lesser power dissipation than a very recently developed adiabatic logic called the Two Phase Clocked Adiabatic Static CMOS Logic (2PASCL). The simulation is carried out in NI-Multisim software at 0.18μm, 1.8V CMOS standard process technology over a frequency range of 200-800 MHz.