Dual signal frequencies and voltage levels for low power clock distribution using thyristor delay

Power consumption by clock distribution network has become an important design consideration as it consumes a major portion of IC power. In present day System on Chips (SoCs) early clock planning leads to better end results when it comes to power consumption. In this paper a methodology based on clock voltage and frequency scaling for lowering the power consumption of the clock distribution system is proposed. A power efficient level converter and frequency doubler has been used to restore the clock levels and frequencies back at the clock leaf node. The proposed circuit was optimized and simulated using Cadence Virtuoso Schematic Composer. It is found that the proposed circuit performs better in terms of power consumption for the same set of signal parameters when we go on from a lower frequency to a higher frequency. The savings can be as high as 35% at lower frequencies to 6% at higher frequencies.