Cyclic codes error correction system based on FPGA

This paper designed and accomplished a codec system of the cyclic code. The encoding system was based on the principle of dividing circuit and the decoding system was based on the principle of Meggitt decoder. There are three main steps in the error correction system which designed for the cyclic code. First, the three binary information codes can be encoded into a group of seven binary codes by using the dividing circuit. Then, the syndrome calculator and spontaneous calculator are used to decode information. The spontaneous calculator can detect an error code word and correct it. Finally, the three binary information codes were successfully encoded and decoded into a group of codes which contain seven binary information. The result of the experiment shows that the cyclic code error correction system can better correct the burst errors and single random error code. It is easy to reach the goal of error-free transmission.