Reducing test time for 3D-ICs by improved utilization of test elevators

A highly efficient test compression scheme for 3D-ICs is proposed, which uses sequential linear decompressors local to each core. The compressed test data is brought from the tester over the test access mechanism (TAM) to the cores where they are decompressed. The idea is to provide flexibility in the utilization of the free variables (i.e., bits stored on the tester that can be assigned 0 or 1), so that the free variables that are not used in one core can be used to encode test cubes in other cores. The decompressors are daisy-chained, such that some of the free variables brought in to one decompressor are passed on to the other decompressors. Consequently, the free variables are also shared with the decompressors in other layers. This enables better utilization of free variables, since free variables not used in one decompressor can be used by any of the other decompressors with which they are shared. The encoding efficiency improves considerably when the free variables are shared with other cores. This reduces test time and tester storage without any additional control. In addition, this architecture also minimizes the number of test elevators required to transfer the test data across layers. The scan chains driven by a decompressor are local to the layer in which the decompressor is present. Hence, only the input to the decompressor, i.e., the compressed test data, is transferred across layers, which reduces the number of test elevators. Furthermore, it is also shown how the number of through-silicon-vias (TSVs)can be reduced further by implementing a test data serializer in the sending layer driving the TSVs and a deserializer converting the serialized data from the TSVs back to the original form.