Advances on the state of the art in QDI design

The ever increasing demand for more complex systems and the possibility of integrating billions of transistors in a single chip brought us to the boundaries of the synchronous paradigm capabilities. The efficient distribution of a global clock signal in a contemporary complex design can be an intricate task and even with the most modern techniques it can consume a significant portion of the total power of a contemporary chip. In fact, according to Amde et al. in [1], clock power represents in average 45% of a synchronous chip total power. Hence, as power budgets get tighter, motivated by battery-based applications demands, and performance gets over constrained by aggressive process variations, traditional design techniques prove to be unsustainable. In this scenario, asynchronous circuits emerge as a promising solution to cope with technological problems faced by synchronous designers and regain the attention of the research community. Asynchronous circuits can be implemented using several templates, each with its own benefits and drawbacks [2]. However, according to Martin and Nyström [3], the most practical template is the quasi-delay-insensitive (QDI). Some of the reasons behind this are that QDI allows simpler timing closure and analysis and can be implemented using cell-based approaches, while maintaining the robustness inherent to asynchronous circuits. However, QDI design flows are scarce and most works available in current literature employ full-custom approaches for implementing such circuits, which inhibits their wider adoption. This work presents a set of advances over the state of the art in QDI design, enabled by the work conducted in the context of the Ph.D. Thesis of the first authors. The main objective of the Thesis is to provide additional levels of automation and optimization in the design of QDI circuits. The contributions of this work can be divided in two main classes: cell library design and circuit synthesis.