A quantum algorithm processor architecture based on register reordering

Quantum computer simulators play an important role when we evaluate quantum algorithms. Quantum computation can be regarded as parallel computation in some sense, and thus, it is suitable to implement a simulator on a hardware, which can process a lot of operations in parallel. In this paper, we propose a processor architecture dedicated to simulating quantum algorithms. The proposed architecture is based on the register reordering method that shifts and swaps registers containing probability amplitudes so that the probability amplitudes of target basis states can be quickly selected. This reduces the number of large multiplexers and improves clock frequency. We implemented the processor on an FPGA. Experimental results show that the proposed processor has scalability in terms of the number of quantum bits, and can simulate quantum algorithms faster than software simulators.