DocumentCode :
1791507
Title :
Towards energy effective LDPC decoding by exploiting channel noise variability
Author :
Marconi, Thomas ; Spagnol, Christian ; Popovici, Emanuel ; Cotofana, Sorin
Author_Institution :
Comput. Eng. Lab., Tech. Univ. Delft, Delft, Netherlands
fYear :
2014
fDate :
6-8 Oct. 2014
Firstpage :
1
Lastpage :
6
Abstract :
In communication systems, channel quality variation is a well known phenomenon, which fundamentally influences the decoding process. While most of the time, the transmission takes place in good signal to noise conditions, to satisfy QoS requirements in all cases, telecom platforms rely on largely over-designed hardware, which may result in energy waste during most of their operation. In this paper we propose to exploit the channel noise variability and adapt the platform operation conditions such that QoS requirements are satisfied with the minimum energy consumption. In particular, we propose a technique to exploit channel noise variability towards energy effective LDPC decoding amenable to low-energy operation. Endowed with the channel noise variability knowledge, our technique adaptively tunes the operating voltage at runtime, aiming to achieve the optimal tradeoff between decoder performance and power con-sumption, while fulfilling the QoS requirements. To demonstrate the capabilities of our proposal we implemented it and other state of the art energy reduction methods in conjunction with a fully parallel LDPC decoder on a Virtex-6 FPGA. Our experiments indicate that the proposed technique outperforms state of the art counterparts, in terms of energy reduction, with 71% to 76% and 15% to 28%, w.r.t. early termination without and with DVS, respectively, while maintaining the targeted decoding robustness. Moreover, the measurements suggest that in certain conditions Degradation Stochastic Resonance occurs, i.e., the energy consumption is unexpectedly diminished due to the fact that unpredictable underpowered components facilitate rather than impede the decoding process.
Keywords :
circuit noise; decoding; energy consumption; field programmable gate arrays; parity check codes; quality of service; DVS; QoS requirement; Virtex-6 FPGA; channel noise variability; channel quality variation; communication system; decoder performance; degradation stochastic resonance; energy consumption; energy effective LDPC decoding; energy reduction method; field programable array; low-density parity-check code; optimal tradeoff; parallel LDPC decoder; power consumption; quality of service; Bit error rate; Decoding; Field programmable gate arrays; Parity check codes; Power supplies; Signal to noise ratio;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Very Large Scale Integration (VLSI-SoC), 2014 22nd International Conference on
Conference_Location :
Playa del Carmen
Type :
conf
DOI :
10.1109/VLSI-SoC.2014.7004180
Filename :
7004180
Link To Document :
بازگشت