Improved read and write margins using a novel 8T-SRAM cell

This paper presents a novel subthreshold 8T-SRAM for ultra-low power applications. The proposed SRAM cell improves write margin by at least 22% to the standard 6T-SRAM cell at supply voltage of 1V compared. Furthermore, read static noise margin is improved by at least 2.2X compared to the standard 6T-SRAM cell. Although by the use of the proposed SRAM cell, the total leakage power is increased for superthreshold regions, the proposed cell is able to work at supply voltages lower than 200mV with significantly improved robustness without any leakage increase. The proposed SRAM design improves write margin of the SRAM cell in comparison to the standard 7T-SRAM cell. The proposed circuit is designed in TSMC 65nm CMOS technology.