Title :
Circuit to reduce Gate Induced Drain Leakage in CMOS output buffers
Author :
Ravi, Hari Anand ; Goel, Mayank ; Bhilawadi, Prasad
Author_Institution :
Intel Mobile Commun. India Pvt. Ltd., Bangalore, India
Abstract :
In recent technology nodes, it has been observed that the leakage current component due to Gate Induced Drain Leakage (GIDL) is a significant contributor towards the overall standby leakage. The circuit proposed in this paper reduces the GIDL current and hence the overall standby power in CMOS output buffers by a factor of ~5.5X. Further, speed of operation of the circuitry is not compromised in the process of reducing GIDL.
Keywords :
CMOS integrated circuits; buffer circuits; CMOS output buffers; GIDL current reduction; gate induced drain leakage reduction; CMOS integrated circuits; Computer architecture; Generators; Logic gates; MOS devices; Microprocessors; Transistors; CMOS output buffer; GIDL; IO; low power;
Conference_Titel :
Very Large Scale Integration (VLSI-SoC), 2014 22nd International Conference on
Conference_Location :
Playa del Carmen
DOI :
10.1109/VLSI-SoC.2014.7004187
