A tool for the automatic TLM-to-RTL conversion of embedded systems requirements for a seamless verification flow

Complex Systems on Chips (SoCs) are built by assembling hardware and software components. SystemC TLM (Transaction Level Modeling) allows to describe SoCs in a very abstract way. From this level, a typical design flow enables the definition of virtual prototypes at different levels of abstraction to support early software development and verification of hardware blocks which, in the last steps, become Register Transfer Level (RTL) models. A compatible and seamless verification flow must give the possibility to verify, along this design flow, that the system requirements remain satisfied. To keep the requirements consistent with the abstraction level, we propose the automatic transformation of system level properties into their counterparts at the RT level. This paper describes a tool for the automatic refinement of temporal assertions from TLM to RT level, using a set of transformation rules. This reuse of TLM assertions is thus the basis of an Assertion-Based Verification (ABV) flow.